A Comparative Analysis Between EPIC Static Instruction Scheduling and DTSVLIW Dynamic Instruction Scheduling

 To achieve performance, Explicitly Parallel Instruction Computing (EPIC) systems take the responsibility of extracting instruction-level parallelism (ILP) from the hardware and give it to the compiler. They expose a large part of the hardware control at the conventional machine level. Dynamically Trace Scheduled VLIW (DTSVLIW) systems, on the other hand, leave the responsibility of extracting ILP to the hardware and use conventional compilers. Their hardware uses a simple hardware implemented scheduling algorithm – executed dynamically – to exploit ILP and achieve performance. This work examines three compiler/EPIC architecture combinations (SGI PRO64 C++ Compiler/IA64, Intel C++ Compiler 5.0.1/IA64 and Trimaran 2.0/HPL-PD) and compares these with a compiler/DTSVLIW architecture combination (gcc/Alpha-DTSVLIW). Our experiments show that, on average, the DTSVLIW architecture achieves better performance than EPIC because its dynamic scheduler, although much simpler, harnesses more ILP due to its exploitation of execution-time information invisible to the EPIC compiler’s scheduler.